1. Field of the Invention
The present invention relates to a logic synthesizer which is for producing a net list which contains information about logic elements consisting of macro cells and designed so as to put significance upon layout simplicity and about connection among them.
2. Description of the Prior Art
FIG. 12 is a block diagram showing an architecture of a prior art logic synthesizer. As shown in FIG. 12, a logic synthesizer 1 takes in a logic function description defining conditions of logic connections from a function description file 5. The function description file 5 is a file which contains logic function description where circuit functions of the logic synthesizer desired by the user are described in HDL (Hardware Description Language).
The logic synthesizer converts the logic function description received from the function description file 5 into a logic such as AND, OR, etc., and it further compresses the logic to produce the optimum logic formula D1 to an optimizing unit 2.
The optimizing unit 2 takes in the logic formula D1 and restricting requirements D7 to a user desired Circuit property described in a restricting requirements file 7. The circuit property herein means a property pertaining to operation velocity, circuit area, demand, etc. In order to gain the circuit property satisfying the restricting requirements D7, the optimizing unit 2 uses macro cells registered in a macro cell library 6 and produces a net list D2 for implementing the logic formula D1 to output it to a fan out regulating unit 3. The macro cells are logic function blocks which are designated and registered in the macro cell library 6 in advance by the user. The net list D2 defines information about logic elements consisting of the macro cells and information about connections among them.
The fan out regulating unit 3 takes in the net list D2, and each macro cell in the net list D2 changes the net list D2 so as to meet fan out restricting requirements registered in the macro cell library 6 and outputs a net list D3 to a timing regulating unit 4.
After taking in the net list D3, the timing regulating unit 4, similar to the fan out regulating unit 3, regulates a timing of a set up time and hold time of a flip flop to change the net list D3 and produces an ultimate net list D4.
Based upon the net list D4, an existing layout unit performs a layout (layout wiring) procedure for macro cells, and .consequently, a logic circuit consisting of macro cells is fabricated.
FIG. 13 is a schematic diagram showing an exemplary layout of macro cells based upon a net list produced by the prior art logic synthesizer (that which is equivalent to the net list D4 in FIG. 1). As shown in FIG. 13, a macro cell (layout) train 8 (consisting of trains 8a, 8b and 8c herein) contain macro cells 10 (10a through 10c, 10d through 10f, 10g through 10i) arranged in the respective trains.
The macro cells 10b and 10d have their respective feedthroughs 11b and 11d, and none of the remaining ones of the macro cells 10 has a feedthrough 11. "Feedthrough" is defined as a wiring traversing region which lies in a macro cell.
Wiring regions 9a and 9b are provided between the macro cell trains 8a and 8b , and 8b and 8c, respectively, and cell connecting wirings 12 (12a through 12d herein) are further provided in the wiring regions 9 to implement a connection between separate macro cells 10.
The prior art logic synthesizer is likely to use, in many cases, macro cells having a small number of or no feedthroughs in designing and structuring a combination circuit because it produces a net list, putting significance upon optimizing a circuit area and an operation velocity. Thus, it is probable that the prior art logic synthesizer produces a net list requiring to have a small number of feedthroughs.
When a logic circuit is structured based upon a net list requiring to have the small total number of feedthroughs, cell connecting wirings formed in a roundabout route in the wiring regions 9 increase in number like a cell connecting wiring 12c connecting between the macro cells 10b and 10h in FIG. 13. As a result, a large wiring load is charged as well as adverse effects such as lack of the intended delay property, etc., are caused; in the worst case, there arises the problem that wirings are left unconnected, and it is impossible to do layout.
Thus, the prior art logic synthesizer has the disadvantage that it produces no net list suitable for a layout procedure.